Verification Engineer sought by ARM Inc. in Chandler, AZ to be part of a small and talented Chandler-based processor RTL design team. Min Req: Master's Degree in Electrical Engineering, Computer Engineering or a related program and 2 years of experience in functional debugging of errors in the RTL model; Verilog HDL language and associated software simulators and waveform debugging tools; Developing detailed verification plans for the block/unit; Generating and running testcases on logic simulation models; Debugging and correcting functional errors in the RTL model, using simulation tools, debug tools, based on in-depth understanding of the architecture and RTL design of the processor; Defining and implementing functional coverage, and enhancing the testbench to ensure coverage closure. Send resume to: firstname.lastname@example.org. Reference #2004.
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